1. Field of the Invention
The present invention relates to a boosting charge pump circuit. In particular, the present invention relates to a boosting charge pump in which it is possible to switch boosting methods of the charge pump circuit which satisfy both DDR1 (double data rate 1) and DDR2 (double data rate 2) specifications, and avoids providing a charge pump capacitance (capacitor for the charge pump) not used in a semiconductor chip.
Priority is claimed on Japanese Patent Application No. 2006-349320, filed Dec. 26, 2006, the content of which is incorporated herein by reference.
2. Description of the Related Art
In a conventional semiconductor memory apparatuses, in order to boost an internal voltage, boosting charge pump circuits of “2×VDD” are applied to memory apparatus of the DDR1 specification which require a high source voltage (external source voltage), and boosting charge pump circuits of “3×VDD” are applied to memory apparatus of the DDR2 specification which require a low source voltage (external source voltage).
It should be noted that DDR2 is the name of a specification which provides better performance and consumes a smaller amount of power than DDR1, and is formulated by JEDEC (Joint Electron Device Engineering Council). There is a conventional DDR specification other than DDR2 that is called DDR1.
FIG. 7 is a drawing showing an example of a constitution of a conventional boosting charge pump circuit that is used for both DDR1 and DDR2 specifications. Details of this circuit are not explained and only an outline of this circuit is explained here because details of a similar boosting charge pump circuit are explained in following embodiments.
In FIG. 7, a constitution is applied in which it is selectable whether or not a capacitor C12 inside the circuit is used by operating connection switching terminals SW11 and SW12.
As shown in the drawing, if the circuit is used in accordance with DDR1 specifications, the connection switching terminals SW11 and SW12 are connected to a side corresponding to DDR1, and the capacitor C12 is disconnected to the circuit in order not to use the capacitor 12C. Moreover, a connection switching terminal SW13 is connected to a side corresponding to DDR1 too.
In the above-described constitution, when a clock signal IN2 indicates “HIGH” (i.e., output of a logically-inverting buffer gate G11 is “LOW”), a capacitor C11 is charged to a voltage level that is the same as the power source voltage VDD by using a NMOS transistor M11.
After that, if the clock signal IN2 is changed to be LOW (i.e., output of a logically-inverting buffer gate G11 is a HIGH level), the voltage at a point (voltage of a point D) to which a drain terminal of the NMOS transistor M12 of the capacitor C11 is connected is boosted so as to be a voltage level of “2×VDD”. After that, a clock signal IN3 is set to HIGH, a NMOS transistor M12 is set to ON, and the output voltage (internal voltage) VPP is generated. Therefore, the internal voltage VPP which satisfies “2×VDD>VPP>VDD” is obtained.
On the other hand, if the circuit is used in accordance with DDR2 specifications, as shown in FIG. 8, both the connection switching terminals SW11 and SW12 are set to connect to a side corresponding to DDR2 in order to connect the capacitor C12 to the circuit. Moreover, both the connection switching terminals SW13 and SW14 are set to connect a side corresponding to DDR2.
In the above-described constitution, when a clock signal IN2 indicates “HIGH” (i.e., output of a logically-inverting buffer gate G11 is “LOW”), a capacitor C12 is charged to a voltage level that is the same as the power source voltage VDD by using an NMOS transistor M13. Here, at the same time, a capacitor C11 is charged to a voltage level so as to be the same as the power source voltage VDD by using an NMOS transistor M11.
After that, if the clock signal IN2 is changed to LOW (i.e., output of a logically-inverting buffer gate G11 is HIGH), the voltage of the capacitor C12 (voltage at a point E) is boosted so as to be a voltage level of “2×VDD”, the voltage of “2×VDD” at the point E is applied to the capacitor C11 via a PMOS transistor (P-Channel MOSFET) M14 and the connection switching terminal SW13, and a voltage at an output side (point D) of the capacitor C11 is boosted so as to be a voltage level of “3×VDD”. After that, a clock signal IN3 is set to HIGH, an NMOS transistor M12 is set to ON, and the internal voltage VPP is generated. Therefore, an internal voltage VPP which satisfies “VPP>2×VDD” is obtained.
The above described boosting charge pump circuit is useful because it is possible to switch between DDR1 and DDR2 specifications only by switching the wiring inside the circuit. However, there is a problem in which there is a charge pump capacitance (charge pump capacitance C12) which is not used after being switched to DDR1 specifications. An area shared by this charge pump capacitance is large and is a waste of chip area on the semiconductor.
It should be noted that in a conventional technique, a booster circuit is introduced (see Patent Document 1). The booster circuit of this conventional technique is provided because of an object of generating a different voltage which is higher than a power source voltage corresponding to usage or a purpose. In order to achieve such an object, the conventional technique provides a first charge pump circuit which boosts a voltage VDD in order to generate a voltage of 2×VDD, a second charge pump circuit which generates a voltage of 3×VDD, a third charge pump circuit which generates a voltage of 4×VDD and a switching portion 4. Based on switching signals, the switching portion 4 outputs a voltage of 3×VDD to an internal circuit of a semiconductor apparatus by serially connecting the first and second charge pump circuits and outputs a voltage of 4×VDD to the internal circuit of the semiconductor apparatus by serially connecting the first, second and third charge pump circuits.
However, the booster circuit of the above-described Patent Document 1 does not provide a solution of the above-described problem in which there is a charge pump capacitor which is not used when the wiring of the boosting charge pump circuit is switched so as to satisfy DDR1 specifications because the conventional technique has an object to obtain predetermined voltages by serially connecting multiple charge pump circuits.
Moreover, a circuit assembly has been proposed which boosts a battery voltage to be two times larger (see Patent Document 2). However, the circuit assembly of Patent Document 2 has an object to provide a circuit assembly which can be satisfactory activated even though the battery voltage is low and/or the temperature is low. The circuit assembly of Patent Document 2 does not provide a solution of the above-described problem in which there is a charge pump capacitor which is not used when the wiring of the boosting charge pump circuit is switched so as to satisfy DDR1 specifications
[Patent Document 1] Japanese Patent Application, First Publication No. 2005-235315
[Patent Document 2] Japanese Patent Application, First Publication No. 2002-112532
As described above, the conventional boosting charge pump circuit is convenient because it is possible to switch between DDR1 and DDR2 specifications by switching the wirings inside the circuit. However, there is a problem in which, when the wiring is switched to DDR1 specifications, there is an unused charge pump capacitance which causes an area of the chip to be wasted.